This invention relates to a memory refresh control system, and more particularly to a refresh control system for memories using dynamic random access memory elements, such as MOS transistors and the like.
Recently, development of such memories shows a tendency to increase their storage capacity. An increase in the storage capacity causes an increase in the number of refresh addresses. A conventional refresh control method for such memories produces, as refresh addresses, addresses respectively corresponding to combinations of n bits in a refresh control circuit, generates, in a limited period of time, refresh clocks corresponding to the respective addresses for specifying 2.sup.n refresh times, and applies the address information and the refresh clocks directly to memory elements to be refreshed.
If the abovesaid prior art refresh control method is applied to a mass storage device with an increased number of refresh addresses, it is necessary that the number of refresh clocks to be sent out in the limited period of time P be increased in correspondence to the increased number of refresh addresses. This inevitably requires a longer refresh time, resulting in reduced efficiency of utilization of the storage device. Further, since the number of bits constituting refresh address data increases, it is required to increase the number of bits for the refresh address data which are sent out from a refresh control circuit provided in a central processor unit. To this end, the central processor unit must be equipped with different interfaces for memories with different numbers of refresh addresses.